فارسی English
ESL Design Methodology and Modeling


دکتر زین العابدین نوابی
دانشکده برق و کامپیوتر،
پردیس دانشکده های فنی، دانشگاه تهران


This course discusses principles, methodologies and tools used for a modern hardware design process. Design flows and hardware languages needed for each stage of the design process are discussed. The course starts with an overview of the evolution of design from transistor level to transaction level. Languages used at each level will briefly be discussed.
We will use C/C++ for description of gates, Boolean level logic circuits, and register-transfer (RT) level components. We start modeling hardware at the logic level and using C++ classes move into descriptions at the register transfer level. We develop a library of C++ classes that will be used for design and description complete RT level designs with datapath and controller. This part of the course highlights shortcomings of procedural languages for describing hardware. We will show how a procedural language like C++ is used for modeling concurrency required in hardware modeling. This leads to the discussion of SystemC that properly handles hardware concurrency through a package of C++ classes and its simulation kernel.
With the embedded concurrency in SystemC, this language can be used for describing hardware at the register transfer level, which is at a higher level of abstraction and suits well for more complex hardware structures than those modeled with C/C++. We will show how SystemC can be used in modeling complex hardware components partitioned into datapath and controllers. While RT level hides many unnecessary hardware details such as gate level timing and load issues, it is still not a proper level for describing today’s complex hardware structures that consist of integration of many IP cores, hard cores, soft cores, and processing elements. SystemC, however, introduces the concepts of channel communication that embeds in it a higher abstraction of communication that hides many RT level details, such as clock level timing, individual word-level transfer, and handshaking. This part leads into discussion of communications and abstract modeling of communication parts. RT level handshaking protocols will be abstracted into SystemC channels and interfaces.
Once communication channels have been discussed and abstract modeling of communications are explained, the course moves into the next level of digital system design and modeling abstraction that is ESL or electronic system level. In this part we use the OSCI standard TLM-2.0. This standard partitions systems into processing elements and communication channels. The concept of describing hardware by dividing it into its computations and communications will be covered. At this level of abstraction, the main concern of a hardware designer is on deciding communications between existing cores and/or hardware or software processing elements. High level communications take place at this level, and data units are often complete data blocks rather than individual words. For describing hardware at the system level, C/C++, SystemC, and the new TLM-2.0 standards are used. C/C++ will be used for describing computations and SystemC TLM-2.0 will be used for modeling communications. TLM-2.0 transport protocol will be used for modeling advanced communication protocols. The methodology takes a hardware designer from specification of a system to TLM-2.0 descriptions with clear hardware correspondence.
After covering languages and techniques for system level design, we discuss several system level architectures that can be described using C++, SystemC, and TLM-2.0. For each architecture the correspondence of TLM-2.0 utilities to an actual hardware at the RT level will be shown. Example applications such as test data compression hardware will be modeled for simulation in C/C++ using SystemC and TLM-2.0 libraries. Based on the methodology that is presented, hardware correspondence for these examples will clearly be defined.
Lectures are ordered to give an introduction to system design, then coverage of C/C++ for logic simulation, this is followed by RTL design and SystemC presentation. TLM-2.0 interfaces, and will be followed by architectures utilizing these interfaces.

1. Digital System Design Automation
  • Transistors to TLM
  • Abstraction levels
  • Embedded system design flow
  • Design tools
  • New hardware design trends
  • Terminologies

2. RTL Logic Design
  • RTL design flow
  • RT level methodology

3. Logic Simulation with C/C++
  • Object oriented logic modeling
  • RT level modeling with C++ procedural language
    o Combinational RTL components
    o Sequential logic
    o Complete RTL systems

4. RT Level Description with SystemC
  • SystemC language structure and basics
    o Module structure
    o Constructors
    o Port declaration
    o Variables, signals, types, and operations
    o Process declaration and registration
    o Events and sensitivity list
    o Interfaces
    o Hierarchies
    o Resolutions
    o Testbench
  • RTL design example
    o Combinational logic
    o Sequential logic
    o A complete example: multiplier

5. Abstract Communications
  • Handshaking procedures
  • Channel communication
  • SystemC channels
    o Primitive channels
    o Hierarchical channels

6. System Level Communications
  • Transaction Level Modeling (TLM 2.0)
    o Generic payload
    o Sockets
    o Transport interfaces
         Blocking transport interface
         Non-blocking transport interface
    o Protocol types

7. System Level Examples in TLM-2.0
  • System Level Architectures
    o Message passing architecture
    o Interconnect-based architecture
  • Test data compression example

بیستمین کنفرانس مهندسی برق ایران

ICEE 2012، تهران، ایران