Power Reduction Techniques in a 6 bit 1 GSPS Flash ADC
Keywords:
Flash ADC, Low power design technique, low Kickback noise, dynamic comparator.
Abstract:
Flash Analog-to-Digital Converters (ADCs) are usuallyused in high-speed yet low-resolution applications such as widebandradio transceivers. Since the power consumption of suchADCs exponentially rises with the number of bits, low-powerdesign techniques are of increasing interest. In this work, thepower consumption of the comparators, the most importantbuilding blocks in such ADCs, have been reduced. First, amodified circuit configuration is proposed where the value of thekick-back noise is remarkably reduced. Then in order to savepower, a power reduction technique is presented based on theprinciple of turning off the preamplifier of the comparators afterthe time when output voltages have been decided using an XORgate. Since the difference of the input voltage with the referencelevel is not very small for most of the comparators in a FlashADC, most of the comparators' outputs are ready before the endof the clock period and thus the proposed idea can save up to40% of the power consumption of the entire ADC. In order toillustrate the effectiveness of the suggested idea, a 6-bit 1GS/sADC is designed and simulated in a 0. 18یm CMOS technology. The circuit consumes 20. 2 mW from a 1. 8-V supply voltage, andthe THD is -32 dB at the input frequency of 200 MHz.